Complementary metal-oxide semiconductor (CMOS) circuits typically include a combination of n-type and p-type field effect transistor (FET) devices. Each FET device includes a source, a drain and a channel between the source and the drain. A gate electrode over and/or surrounding the channel regulates electron flow between the source and the drain.
As feature sizes of CMOS circuits get increasingly smaller (commensurate with current technology) a number of challenges arise. For instance, scaling brings about issues related to electrostatics and mobility degradation in CMOS devices. A finFET architecture offers increased scaling opportunities beyond that attainable with planar devices. See, for example, B. Yu et al., “FinFET Scaling to 10 nm Gate Length,” IEDM (2002). FinFET devices exhibit fast switching times and high current densities.
However, some key technical challenges still have yet to be overcome with CMOS device scaling. One challenge is gate length scaling (and maintaining performance while doing so). Another is lithography at increasingly scaled dimensions.
Thus, techniques that permit gate length scaling without performance degradation and a more uniform CMOS circuit structure to pattern with lithography would be desirable.